The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device for communication processing and to a semiconductor integrated circuit device having an A/D (analog-to-digital) converter.
An A/D converter (ADC) is disclosed in each of the following four non-patent documents: T. Oshima, et al., “Fast nonlinear deterministic calibration of pipelined A/D converters,” IEEE 2008 Midwest Symposium on Circuits and Systems, Session C2L-C-1, August 2008; T. Oshima, et al., “23-mW 50-MS/s 10-bit pipeline A/D converter with nonlinear LMS foreground calibration,” 2009 International Symposium on Circuits and Systems, pp. 960-963, May 2009; J. Mcneill, et al., “A split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC,” IEEE 2005 International Solid-State Circuits Conference, pp. 276-277, February 2005; W. Liu et al., “A 12b 22.5/45 MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR,” IEEE 2010 International Solid-State Circuits Conference, pp. 380-381, February 2010. An ADC includes an A/D conversion unit (ADCU) which receives an analog signal and a digital correction unit (DCU) which receives the output of the ADCU. An ADC including such an ADCU and a DCU can operate at high speed with high accuracy with low power consumption.